Static timing analysis (STA) is used throughout chip design. It’s employed for the creation of basic constraints in synthesis, for block- and chip-level timing closure in physical implementation, and ...

About five years ago if you listened to the marketing messages in the EDA industry, you would have thought it would be impossible to produce chips without statistical static timing analysis (SSTA).

SAN MATEO, Calif. — Sequence Design Inc. has introduced a static timing analysis tool that accounts for inductance delay and IR drop in ASICs and system-on-chip designs. In addition, the company has ...

Static Timing Analysis (STA) not only acts as a connecting link between backend and frontend design activities, but more importantly helps in bridging the gap between simulation and silicon. STA is ...

Have you ever wondered how a predator succeeds or its prey escapes in the jungle? It’s the breathtaking speed and agility of the predator (say, a leopard) as it chases prey (say, a deer). The VLSI ...

Statistical static timing analysis (SSTA)—theory, thesis project, IBM proprietary technology—is about to add one more stage to its evolution: mainstream member of the design flow. For some time now ...