Electronic Design

Automotive design example illustrates hierarchical DFT architecture

Fort Worth, TX. Designs keep scaling and taking on a lot of complexity, according to Ron Press, technology enablement director at Mentor Graphics. Delivering a corporate presentation Wednesday on the ...
Semiconductor Engineering

Power-Aware Test: Addressing Power Challenges In DFT And Test

Integrated circuit (IC) sizes continue to grow as they meet the compute requirements of cutting-edge applications such as artificial intelligence (AI), autonomous driving, and data centers. As design ...
Electronic Design

What’s Next for Physically Aware DFT?

Why isolated flows negatively impact design schedule and PPA. Benefits of unified DFT, synthesis, and physical design flows. Physical implementation optimization methods for test compression and scan ...
Semiconductor Engineering

Smart Plug-And-Play DFT For Arm Cores

Modern SoCs are experiencing continued growth in capabilities and design sizes with more and more subsystem IPs being implemented. These large, complex, multi-core SoCs need strategies for DFT and ...
EDN

Filter banks, part 2: Optimization and synthesis

Before we proceed, let's quickly review our filter bank example. Our example, shown in Figure 1, is a size 16 DFT filter bank. The color scheme shows the sample rate change where a 16 MHz input sample ...