EDN

Gate level simulations: verification flow and challenges

Simulations are an important part of the verification cycle in the process of hardware designing. It can be performed at varying degrees of physical abstraction: In many companies RTL simulations is ...
Semiconductor Engineering

Get To Know The Gate-Level Power Aware Simulation

The post-synthesis gate-level netlist (GL-netlist) based PA simulation input requirements are mostly the same as RTL simulation. However, the design under verification here is the GL-netlist from ...
Semiconductor Engineering

Writing Reusable UPF For RTL And Gate-Level Low Power Verification

The Unified Power Format (UPF) is used to specify the power intent of a design. Once written, the UPF file is applied at every stage of the design cycle — starting with the RTL, then the gate-level, ...
EDN

Reuse UVM RTL verification tests for gate level simulation

When we verify a System on Chip (SoC) that embeds microprocessors with several digital peripherals, and possibly analog blocks as well, we want to check all the implemented features and possible ...
Electronic Design

Instant "Replay" Comes To Timing Simulation

Many designers continue to perform timing simulation for gate-level designs. Through an add-on module for its Siloti Visibility Enhancement software, Novas Software now brings timing-accurate ...
Design-Reuse

Avery Design Systems Unveils SimXACT for Elimination of X Pessimism Issues in Gate-Level Simulation and Upgrades XVER X Verification

ANDOVER, Mass.-- March 23, 2012--Avery Design Systems Inc., an innovator in functional verification productivity solutions, today announced availability of its revolutionary X verification solution, ...
Design-Reuse

Mixed-Signal Verification Methodology Using Nanosim Integration with VCS

With gate counts and system complexity growing exponentially, new submicron technologies pose many challenges in both the design and verification domains. Nowadays, many high-performance ...