Duke Pratt School of Engineering

Study Finds Next-Generation Transistor Performance Inflated in Most Lab Testing

Duke engineers show how a common device architecture used to test 2D transistors overstates their performance prospects in real-world devices.
Nanowerk

Common lab design inflates 2D transistor performance by up to six times

Lab architecture used to test 2D semiconductors artificially boosts performance metrics, making it harder to assess whether these materials can truly replace silicon.
Electronic Design

Test Setup Checks Transistors’ hFEs When Tight Control Is Important

This file type includes high resolution graphics and schematics. The spread of h FE values in a batch of transistors may be wide enough to cause unreliable performance during mass production of a ...