EDN

Low power LDPC decoder created using high level synthesis

HLS methodology allows the hardware design to be completed at a higher level of abstraction such as C/C++ algorithmic description. This provides significant time and cost savings, and paves the way ...
Nature

Dynamic Scheduling and Decoding Algorithms for LDPC and Reed-Solomon Codes

Dynamic scheduling and decoding algorithms have become pivotal in advancing the performance of error-correcting codes. Recent innovations have focused on refining Low-Density Parity-Check (LDPC) codes ...
Design-Reuse

Creonic to Supply New LDPC Decoder and Encoder IP Cores for CCSDS Standard

Kaiserslautern, Germany, Apr. 30 2015 – Creonic GmbH, a leading IP core provider for communications, announced today the release of their new CCSDS LDPC encoder and decoder IP cores for the satellite ...
Design-Reuse

Creonic Introduces 25 Gbit/s LDPC IP Core Solution for ITU G.9804.2 PON Standard

Kaiserslautern Germany -- May 10, 2023 - Creonic GmbH, a leading IP core provider in the field of satellite communications, today introduced its latest LDPC forward ...
insideHPC

AccelerComm Unveils Integrated PUSCH Decoder for 5G NR

Southampton, UK and MWC Shanghai, China – 18 th February 2020: AccelerComm, the channel coding specialist, has announced Physical Layer IP for 5G NG designed to increase spectral efficiency and reduce ...
EDN

LDPC: Another Key Step Toward Shannon

For communication designers, especially those in the networking and wireless field, the Shannon limit can be seen as the Holy Grail. And, since being first defined in ...
Electronic Design

Low-Density Parity Check Error Correction for Solid State Storage

Error Correcting Code (ECC) technology, such as Low-Density Parity Check codes, has been around longer than most of you reading this have been alive. The reason is ...