ATPG targets faults at IC-gate boundaries, but 50% of defects are located within cells. Learn how cell-aware ATPG and user-defined fault models help to ferret out these hard-to-squash bugs.
Fault simulation, one of the oldest tools in the EDA industry toolbox, is receiving a serious facelift after it almost faded from existence. In the early days, fault simulation was used to grade the ...
Once IC fabrication is complete, engineers use fault models to create test patterns that detect defects. These fault models are typically abstractions of defect behavior based on our experience and ...
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