EDN

Phase/frequency detectors

Two ECL three-state phase/frequency detectors have been designed to be used in PLLs, clock management, and various broadband communication signal synchronization applications. Packaged in a 20-pin ...
EDN

Frequency and phase locked loops

The purpose of a phase locked loop (PLL) is to generate a frequency and phase-locked output oscillation signal. To achieve this goal, prior art essentially functioned ...
Design-Reuse

Low Power High Speed All Digital Phase Locked Loops

In this paper an All Digital phase locked loop is proposed. This PLL can accomplish faster phase lock. Additionally, the functions of frequency comparator and phase detector have been improved and are ...
Design-Reuse

Phase-frequency detector in ECL logic

The phase-frequency detector (PFD) consists of 2 D-trigger with reset from external circuit, performed in ECL logic and multiplexer, which allow to sw ...