EDN

Verifying large models in RTL simulation

Verifying that a multi-million gate ASIC will function according to its specification prior to being built into a system composed of hundreds or thousands of additional ASICs plus thousands of other ...
Semiconductor Engineering

Distributing RTL Simulation Across Thousands Of Cores On 4 IPU Sockets (EPFL)

“Hardware development relies on simulations, particularly cycle-accurate RTL (Register Transfer Level) simulations, which consume significant time. As single-processor performance grows only slowly, ...
Business Wire

Aldec® Delivers $1,995 Mixed Language Simulator to FPGA Market

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a leader in RTL simulation and Electronic Design Automation (EDA), unveils a new low-cost mixed language RTL simulator -- Active-HDL™ Designer Edition.
Design-Reuse

Aldec Introduces Hardware Assisted RTL Simulation Acceleration for Microchip FPGA Designs

The latest release of HES-DVM™ provides a simulation acceleration flow, providing significant RTL simulation speed-up of designs targeting Microchip FPGA devices. Henderson, NV, USA – November 3, 2020 ...
Semiconductor Engineering

Getting A Handle On RTL X-Verification Challenges

The problem logic designers have with X’s is that RTL simulation is optimistic in behavior and this can hide real bugs in your design when you go to tapeout. Some engineers point out that we have ...
EDN

Modeler connects RTL, SystemC simulation

SAN JOSE, Calif. — Adding a proverbial tiara to its Miss Univers line of hardware/software co-verification tools, Adveda Inc. is introducing this week a model generator simulation add-on that places a ...
Hackaday

Exploiting Hardware-Level Parallelism In The Manticore Hardware-Accelerated RTL Simulator

Before a chip design is turned from a hardware design language (HDL) like VHDL or Verilog into physical hardware, testing and validating the design is an essential step. Yet simulating a HDL design is ...
New Electronics

Making RTL verification easier

Codasip, a supplier of customisable RISC-V embedded processor IP, and Metrics Design Automation, a provider of the True Cloud EDA solution, have announced the integration of Metrics’ SystemVerilog RTL ...
Design-Reuse

Codasip and Metrics Design Automation Announce the Integration of the Metrics Cloud Simulation Platform in Codasip's RISC-V SweRV CORE Support Package Pro

Munich, Germany and Ottawa, Canada – August 5 th 2020 – Codasip, the leading supplier of customizable RISC-V embedded processor IP, and Metrics Design Automation, providers of the only True Cloud EDA ...
Embedded

Static timing analysis: bridging the gap between simulation and silicon

Static Timing Analysis (STA) not only acts as a connecting link between backend and frontend design activities, but more importantly helps in bridging the gap between simulation and silicon. STA is ...
Business Wire

Aldec Introduces Hardware Assisted RTL Simulation Acceleration for Microchip FPGA Designs

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed-HDL language simulation and hardware-assisted verification for ASIC and FPGA designs, has introduced a HES-DVM™ simulation ...