Have you ever wondered if there’s a way to break free from the dominance of proprietary computing architectures like x86 and ARM? For decades, these platforms have dictated the rules of the game, ...
The RISC-V Summit North America, held on 22-23 October 2025 in Santa Clara, California, showcased the latest CPU cores featuring new vector processors, high-speed interfaces, and peripheral subsystems ...
The 2024 RISC-V Summit North America marked a significant milestone for the RISC-V community with the ratification of the RVA23 Profile. This event signifies a major step forward in the evolution of ...
When the number two provider of CPU designs jumps on the RISC-V train, it is a significant milestone. The open-source RISC-V design is on a roll, displacing Arm in many SoC development plans. ARC and ...
RISC-V cores are beginning to show up in heterogeneous SoCs and packages, shifting from one-off standalone designs toward mainstream applications where they are used for everything from accelerators ...
RISC-V, the open-standard Instruction Set Architecture (ISA) conceived by UC Berkeley developers in 2010, is going from strength to strength. The RISC in RISC-V stands for Reduced Instruction Set ...
RISC-V chip design and IP powerhouse, SiFive, just announced availability of its new HiFive Premier P550 development board, and it's sure to make waves at the RISC-V Summit this week in Santa Clara.
The Android Common Kernel is about to remove support for the RISC-V architecture. Android Common Kernel is Google’s fork of the upstream Linux kernel but with Android-specific additions. RISC-V is an ...
With the rise of RISC-V architecture, developers are seeking efficient and flexible solutions for their processor needs. MIPS RISC-V IP Core Technology is at the forefront of this revolution, offering ...
Last year computer maker Framework announced plans to release a RISC-V Mainboard for its 13 inch laptops. Then the company launched an early access program in November. And now the DeepComputing ...
If you read Japanese, you might have seen the book “Design and Implementation of Microkernels” by [Seiya Nuda]. An appendix covers how to write your own operating system for RISC-V in about 1,000 ...
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